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Thu Oct 11, 2007 10:11 pm
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Public Announcements
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| IC DFT Topics |
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Scan Design
Scan cell design, Scan architecture, Scan chain configuration, Scan chain ordering/reordering, Full vs Partial sca
Moderators siyad, John Ford |
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30 |
Wed Aug 20, 2008 3:17 am
sbr |
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ATPG and Fault Simulation
ATPG algorithms, Fault simulation algorithms, fault models, fault classes, fault coverage
Moderators siyad, John Ford |
25 |
71 |
Tue Aug 19, 2008 10:36 pm
shakti_pattnaik |
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Test Compression
Compression methods, test length reduction, test volume reduction, test compactors, X-tolerance
Moderators siyad, John Ford |
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7 |
Tue Aug 19, 2008 5:13 am
srmprakash |
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Transition and Delay Fault
Transition fault, path delay fault, gate delay fault, small delay defects, robust vs non-robust vs hazard free tests, spot delay defects, process variations
Moderators siyad, John Ford |
3 |
9 |
Wed Apr 30, 2008 2:13 am
ashutosh |
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Memory/Array Test
Memory test, Memory BIST, DRAM test, CAM test, BIST algorithms, Memory Faults, Redundancy and Repair
Moderators siyad, John Ford |
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21 |
Tue Aug 19, 2008 12:17 am
sbr |
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Logic BIST
LFSR/MISR/CA based, test length, pseudo-random, weighted random, aliasing
Moderators siyad, John Ford |
5 |
11 |
Tue Aug 19, 2008 12:18 am
sbr |
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High Speed IO Test
GHz/Gbps interface test, jitter and noise, eye diagram, source synchronous clocks, clock recovery, high speed instrumentation and measurement
Moderators siyad, John Ford |
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Core Test
Core-based testing, IP testing, isolation ring, test protocols, IEEE 1500
Moderators siyad, John Ford |
1 |
4 |
Wed Mar 12, 2008 8:16 pm
John Ford |
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JTAG and Boundary Scan
IEEE 1149.1, IEEE 1149.6, BSDL, SJTAG, iJTAG, cJTAG
Moderators siyad, John Ford |
8 |
25 |
Tue Aug 19, 2008 7:44 am
sbr |
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Current Test
IDDQ, IDDx, current measurement devices, on-chip current monitors, DFT for low power designs
Moderators siyad, John Ford |
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Analog and Mixed Signal Test
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Others
Other DFT concepts/topics
Moderators siyad, John Ford |
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9 |
Wed May 14, 2008 7:56 pm
dft_05 |
| Board and System DFT Topics |
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Board DFT
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System DFT
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| DFT Tools |
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Commercial Tools
Tool features, tool releases, tool comparisons
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Academic Tools
New tool research, academic DFT tool releases, benchmark circuits
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Public Domain Tools
Any DFT releated tool that is free!
Moderators siyad, John Ford |
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| Other Technical Topics |
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Physical Design
Effect of DFT on synthesis and timing, synthesis/timing flows for DFT logic, Place and Route of DFT logic, DFT for custom designs
Moderators siyad, John Ford |
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3 |
Mon Mar 17, 2008 9:32 pm
vani |
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Package Design
Pin assignment and placement, signal integrity
Moderators siyad, John Ford |
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IC Manufacturing
DFM, yield prediction, yeild enhancement
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Silicon Debug
Debug features, diagnostic tools, failure analysis
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IC Quality
Burn-in, accelerated life test, infant mortality, ESD
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IC and System Reliability and Availability
Fault tolerance, soft errors, error detecting/correcting codes, rediation hardened devices, redundancy schemes, voting systems
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| Miscellaneous |
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DFT Job Hotline
Post job opennings and resumes here!
Moderators siyad, John Ford |
2 |
3 |
Thu May 22, 2008 2:25 am
ahfoo |
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DFT Humor and Facts
Jokes, Riddles, Quizzes, Interesting facts, Interview questions, etc.
Moderators siyad, John Ford |
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Forum Test
Use this forum to test posting from your account. Please report any errors to admin@design-for-test.com
Moderators siyad, John Ford |
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Sat Oct 13, 2007 5:47 pm
siyad |
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